1module alu_16bit (
2 input [15:0] A,
3 input [15:0] B,
4 input [3:0] op,
5 output reg [15:0] result,
6 output reg [3:0] flags // {V, N, C, Z}
7);
8
9 wire [16:0] sum = {1'b0, A} + {1'b0, B};
10 wire [16:0] diff = {1'b0, A} - {1'b0, B};
11
12 always @(*) begin
13 result = 16'b0;
14 flags = 4'b0;
15 case (op)
16 4'b0000: result = sum[15:0]; // ADD
17 4'b0001: result = diff[15:0]; // SUB
18 4'b0010: result = A & B; // AND
19 4'b0011: result = A | B; // OR
20 4'b0100: result = A ^ B; // XOR
21 4'b0101: result = ~A; // NOT
22 4'b0110: result = A << 1; // SHL
23 4'b0111: result = A >> 1; // SHR
24 default: result = 16'b0;
25 endcase
26
27 // Flag generation
28 flags[0] = (result == 16'b0); // Z (Zero)
29 flags[1] = (op == 4'b0000) ? sum[16] : diff[16]; // C (Carry/Borrow)
30 flags[2] = result[15]; // N (Negative)
31 flags[3] = 1'b0; // V (Overflow) - simplified
32 end
33
34endmodule